1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing a liquid crystal display (LCD) device.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, many efforts and studies are being made to develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as a substitute for CRTs. Of these flat panel displays, LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and face each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes in accordance with the intensity of the induced electric field into the direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
FIG. 1 is a schematic plan view illustrating an array substrate of an LCD device according to the related art.
Referring to FIG. 1, the array substrate includes a gate line 20 and a data line 30 crossing each other to define a pixel region P on a substrate 10. A thin film transistor T is in the pixel region P and connected to the corresponding gate and data lines 20 and 30. The thin film transistor T includes a gate electrode 25, a semiconductor layer, and source and drain electrodes 32 and 34. The semiconductor layer includes an active layer 40 of intrinsic amorphous silicon and an ohmic contact layer of impurity-doped amorphous silicon.
A pixel electrode 70 is in the pixel region P and connected to the thin film transistor T. The pixel electrode 70 is connected to the drain electrode 34 through a drain contact hole CH1 exposing the drain electrode 34.
FIGS. 2A to 2G are cross-sectional views, taken along a line II-II of FIG. 1, illustrating processes of manufacturing the array substrate of FIG. 1.
Referring to FIG. 2A, a metal layer is deposited on a substrate 10. The substrate 10 includes a switching region S, a pixel region P and a data region D. The metal layer is patterned with a first mask to form a gate line (20 of FIG. 1) and a gate electrode 25. The gate electrode is formed in the switching region S. The metal layer is made of one of copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy, chromium (Cr). A gate insulating layer 45 is formed on the substrate 10 having the gate electrode 25.
Referring to FIG. 2B, an intrinsic amorphous silicon layer and an impurity-doped amorphous silicon layer are formed on the gate insulating layer 45 and patterned with a second mask to form an active layer 40 and an ohmic contact layer 41 on the active layer 40. A semiconductor layer 42 includes the active layer 40 and the ohmic contact layer 41.
Referring to FIG. 2C, a metal layer 75 and a photoresist layer 80 are sequentially deposited on the substrate 10 having the semiconductor layer 42. The metal layer 75 is made of one of copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy, chromium (Cr).
A third mask is over the photoresist layer 80. The third mask includes a transmissive portion T1 and a blocking portion T2. The photoresist layer 80 may be a positive type photoresist. The transmissive portion T1 is located between the blocking portions T2 corresponding to the switching region S. Further, the blocking portion T2 is located corresponding to the data region D.
Referring to FIG. 2D, a light exposure process and a developing process are performed for the photoresist layer (80 of FIG. 2C) to form first to third photoresist patterns 81 to 83. A distance CD 1 between the first and second photoresist patterns 81 and 82 is about 5 μm which is the same as a design value of the third mask.
Referring to FIG. 2E, the metal layer (75 of FIG. 2D) is wet-etched using the first to third photoresist patterns 81 to 83 as an etching mask to form source and drain electrodes 32 and 34 and a data line 30. When the metal layer is made of one of copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy, chromium (Cr), the metal layer can not be dry-etched, the metal layer is thus wet-etched. A hydrogen peroxide (H2O2) group etching solution is used as an etchant for the metal layer. However, in the wet-etching process, the etchant may flows below side portions of the first and second photoresist patterns 81 and 82, thus over-etching may occur for the metal layer. This over-etching causes widths of the source and drain electrodes 32 and 34 and the data line 30 to be reduced. Accordingly, a distance CD2 between the source and drain electrodes 32 and 34 is more than the distance CD1 which is a desired distance between the source and drain electrodes 32 and 34.
Referring to FIG. 2F, the ohmic contact layer 41 is dry-etched using the source and drain electrodes 32 and 34 as an etching mask. Through the dry-etching process, the separated ohmic contact layers 41 are formed, and a distance between the ohmic contact layers 41 is the distance CD2 between the source and drain electrodes 32 and 34. Accordingly, the distance CD2 is desired to be about 5 μm, but the distance CD2 increases at each of both sides by about 1 μm. In other words, the distance CD2 becomes about 7 μm.
A portion of the active layer 40 corresponding to the distance CD2 is referred to as a channel portion CH. Because of the over-etching of the source and drain electrodes 32 and 34, a length of the channel portion CH increases more than designed. As a result, the over-etching causes change of the length of the channel portion CH, thus property of a thin film transistor is degraded.
After the dry-etching, the first to third photoresist patterns (81 to 83 of FIG. 2E) are stripped.
Referring to FIG. 2G, a passivation layer 55 is formed on the substrate 10 having the source and drain electrodes 32 and 34. The passivation layer 55 is patterned with a fourth mask to form a drain contact hole CH1 exposing the drain electrode 34.
A transparent conductive layer is formed on the passivation layer 55 and patterned with a fifth mask to form a pixel electrode 70. The pixel electrode 70 is connected to the drain electrode 34 through the drain contact hole CH1.
Through the above processes, the array substrate is manufactured. As described above, because of the over-etching in the wet-etching process of the source and drain electrodes, the length of the channel portion increases. Accordingly, the property of the thin film transistor is degraded, and display quality of the LCD device is thus degraded.